Delta sigma modulators provide analog to digital (A/D) conversion with high resolution. Such modulators (also known as sigma delta modulators) provide A/D conversion by employing a combination of oversampling techniques and noise shaping techniques U.S. Pat. No. 4,588,981, entitled "Double Integration, Delta Sigma, Analog Digital Coder", issued on May 13, 1986 to Senn, provides a detailed discussion of one such delta sigma modulator. The delta sigma modulator described in that patent is depicted in FIG. 1.
The delta sigma modulator 10 of FIG. 1 includes an input 12 to which an analog input E(P) is applied. Typically, the analog input E(P) has a frequency ranging from DC to several kilohertz. The delta sigma modulator 10 is provided with an inverting switched capacitor circuit 67 (i.e., switches 28, 30, 32, 34 and capacitor C3) that oversamples the analog input, typically at a rate ranging from several kilohertz to several megahertz.
The delta sigma modulator 10 also includes a first integrator 18 formed from an amplifier 19 and an integration capacitor C5. The non inverting input of the amplifier 19 is tied to ground, whereas the inverting input is coupled to inverting switched capacitor circuit 67 and to an additional inverting switched capacitor circuit 63. The additional inverting switched capacitor circuit 63 includes switches 36 38, 40 and 42 and a capacitor Cl. This additional inverting switched capacitor circuit 63 samples the output signal S(P) of the modulator 10 and feeds back corresponding charge packets to the integration capacitor C5. The central role of circuit 63 is as a feedback mechanism that helps to stabilize the modulator 10.
The first integrator 18 produces an output corresponding to the amount of charge dumped from capacitors C3 of circuit 67 and Cl of circuit 63 onto the integration capacitor C5. The delta sigma modulator 10 also includes a second integrator 20 comprised of a second operational amplifier 64 and a second integration capacitor C8. Inverting switched capacitor circuit 61 forwards a signal to the inverting input of the amplifier 64. The mean amplitude of this signal is proportional to the amplitude of the output signal S(P). Inverting switched capacitor circuit 61 comprises switches 15, 17, 19 and 21 and capacitor C4. The non-inverting input of the amplifier 64 is tied to ground.
The second integrator 20 is preferably used in conjunction with switched capacitor circuit 61 and a switched capacitor circuit 93 as a filter that cooperates with the first integrator 18 to shape the noise at the output of the modulator, to facilitate later digital filtering of the output. The switched capacitor circuit 93 includes switches 52, 54, 60 and 62 and capacitor C2. This switched capacitor circuit 93 passes a signal from the output of the first integrator 18 onto the inverting input of the amplifier 64.
The output of the second integrator 20 is connected to the D input of a quantization circuit, realized in FIG. 1 as a D type flip flop 73. The reference voltages +V.sub.ref and -V.sub.ref are applied to the D flip-flop 73 and constitute the possible values of the S(P) output signal. The clock input Ck of the flip-flop 73 receives a timing signal H.sub.2, provided by a timing circuit 69 which determines S(P) (i.e., +V.sub.ref or -V.sub.ref). The digital output signal S(P) is produced from the inverted output Q* of flip flop 73.
The operation of delta sigma modulator 10 will be explained with reference to FIG. 2. Initially, at time T.sub.1, timing circuit 69 sets control signal H.sub.1 high. For the present discussion, when a control signal is high, the switch receiving the control signal is closed, and when the control signal is low, the switch is open. Hence, in circuit 67, switches 28 and 34 close in response to the high level of control signal H.sub.1. Switches 30 and 32, on the other hand, are responsive to control signal H.sub.2, which is set low by timing circuit 69 at time T.sub.1 ; accordingly, switches 30 and 32 are open. This switch configuration causes the capacitor C3 to be charged to the level of the voltage of the analog input. At time T.sub.2 switches 28 and 34 are opened by timing circuit 69 setting control signal H.sub.1 low, while switches 30 and 32 are closed by timing circuit 69 setting control signal H.sub.2 high. This switch configuration causes the voltage across capacitor C3 to be impressed on the summing node VN1.
The control signals H.sub.1 and H.sub.2 issued by the timing circuit 69 also control the switches in circuit 63. For the circuit 63, switches 36 and 42 are controlled by the control signal H.sub.1, whereas switches 38 and 40 are controlled by the control signal H.sub.2. Hence, at time T.sub.1, capacitor Cl begins charging and at time T.sub.2, capacitor C.sub.1 begins discharging. Thus, these control signals control the timing of the switches in these circuits 63 and 67 so that capacitor C3 and capacitor Cl charge and discharge together. It is, thus, apparent that, for each clock cycle, sampling of the input and the feedback occurs during the phase when H.sub.1 is high and dumping of the sampled packets of charge occurs during the phase when H.sub.2 is high. This scheme provides a time frame equal to the time when H.sub.1 is high for the capacitors Cl and C3 to charge to the appropriate level.
Since both circuits 63 and 67 dump packets of charge onto the integration capacitor C5, the output produced from the first integrator 18 is indicative of the net charge that these circuits dump onto capacitor C5. In particular, since the non-inverting input of the amplifier 19 is tied to ground, this configuration provides an output signal that is proportional to the integral of the voltage at the input of the integrator 18. Accordingly, the output will reflect the cumulative effect of the charge packets of the sampled analog input and the charge packets fed back into the first integrator 18 from switched capacitor circuit 63.
Output from the integrator 18 is sampled by inverting switched capacitor circuit 93. The timing of the operation of the inverting switched capacitor circuit 93 is synchronized with the timing of the operation of the circuit 61. Specifically, at time T.sub.1 (see FIG. 2), switches 52 and 60 are open (because control signal H.sub.2 is low) while switches 54 and 62 are closed (because control signal H.sub.1 qoes high). This switch configuration causes the discharging of the capacitor C2. At time T.sub.2, however, switches 52 and 60 are closed by control signal H.sub.2 going high, whereas switches 54 and 62 are opened by asserting control signal H.sub.1 low. In this switch configuration, capacitor C2 charges.
The output from inverting switched capacitor circuit 93 is supplied to the inverting input of amplifier 64 of the second integrator 20. Also connected to this inverting input is the output from inverting switched capacitor circuit 61 at a second summing node VN2. This circuit 61 comprises switches 15, 17, 19 and 21 and capacitor C4. Its control timing signals are synchronized with timing signals of input sampling circuit 93. Capacitor C2 and capacitor C4 begin charging at time T.sub.2 and begin discharging at time T.sub.4 when H.sub.1 qoes high again. The output produced from the circuit 61 has a mean amplitude that is proportional to the mean amplitude of the output S(P).
The second integrator 20 receives the charges from circuits 6 and 93. It produces an output indicative of the amount of charge that is passed to it. The resulting output signal is passed to the D type flip flop 73 wherein the output signal is quantized to produce the signal S(P).
The capacitances of capacitors Cl and C3 dictate the size of the switches employed in the circuits 63 and 67, respectively. Specifically, the switches must be large enough to handle the amount of charge that is accumulated and discharged on the capacitors. Since the capacitances of capacitors Cl and C3 dictate the amount of charge dumped to the integrator 18, these capacitances also affect the current drive requirements of the amplifier that is employed.
It is, therefore, an object of the present invention to decrease the capacitances of the capacitors used to sample the analog input.
It is another object of the present invention to decrease the capacitances of the capacitors used to sample the reference voltage.
It is yet another object of the present invention to decrease current drive requirements of the amplifier of the first integrator.
It is a final object of the present invention to decrease the size of switches employed within the switched capacitor circuits that sample the analog input and reference voltage.